With the rapid development of semiconductor packaging techniques, semiconductor devices are brought to the market in various package types. In a process to manufacturing a semiconductor device, first a semiconductor chip is installed on a package substrate or a lead frame, then the semiconductor chip is electrically connected to the package substrate or the lead frame, and finally an encapsulant is covered on the semiconductor chip and the package substrate or the lead frame. A ball grid array (BGA) technique is one of the most advanced semiconductor packaging techniques. The BGA technique includes installing a semiconductor chip on a package substrate, and installing a plurality of array disposed solder balls on a rear surface of the package substrate by using a self-alignment technique. Therefore, a number of I/O connection terminals per unit area on a carrying member carried with the semiconductor chip is increased, and an integration demand for semiconductor chips is requested. The semiconductor chip is electrically connected via these solder balls to external devices.
The semiconductor packaging technique of the prior art, when manufacturing the semiconductor device, first adheres the semiconductor chip to a front surface of the package substrate, then performs wire bonding or flip chip packaging process on the semiconductor chip, and finally installs on the rear surface of the package substrate the solder balls, which electrically connect the semiconductor chip to the external devices. Although the semiconductor device manufactured by such a semiconductor package technique has increased number of I/O connection terminals and meets the requirement of high pin count, the electric characteristics of the semiconductor device, when operating at a high frequency, are severely restricted due to too long a conductive connection route. Moreover, the semiconductor packaging technique of the prior art needs to perform many times of connecting interface processes, so that a manufacturing process for the semiconductor device is complicated.
In order to solve the drawbacks of the prior art, R&D personnel for the semiconductor device try not to install the semiconductor chip on the package substrate, but embed the semiconductor chip into the package substrate instead, to shorten the conductive connection route, reduce signal loss and distortion, and improve the performance of the semiconductor device while operating at the high frequency.
FIG. 1 is a cross sectional view of a package member having a substrate embedded with semiconductor chips according to the prior art. The package member comprises a carrying board 10. At least a cavity 100a is formed on a surface 100 of the carrying board 10. The package member further comprises at least a semiconductor chip 11 installed on the carrying board 10 and received in the cavity 100a. A plurality of electrode pads 110 are formed on the semiconductor chip 11. The package member further comprises a circuit build-up structure 12 formed on the carrying board 10 and electrically connected via a plurality of conductive vias 120 to the electrode pads 110.
The semiconductor chip 11 comprises an active surface 11a and a non-active surface 11b opposing to the active surface 11a. The electrode pads 110 are installed on the active surface 11a. The non-active surface 11b is formed in the cavity 100a and adhered to the carrying board 10 by the use of an adhesive 13.
The circuit build-up structure 12 comprises at least a dielectric layer 121, a circuit layer 122 interlacing with the dielectric layer 121, and a plurality of conductive vias 120 passing through the dielectric layer 121 and electrically connected to the circuit layer 122 and the electrode pads 110. A plurality of electric connection terminals 123 are further formed on an outmost surface of the circuit layer 122 of the circuit build-up structure 12. A solder mask 124 is further formed on the outmost surface of the circuit layer 122. The solder mask 124 comprises a plurality of openings for exposure of the electric connection terminals 123. The electric connection terminals 123 are installed for plantation of a plurality of conductive elements such as solder balls 125. Therefore, the semiconductor chip 11 installed on the carrying board 10 and received in the cavity 100a can be electrically connected via the electrode pads 110, the circuit build-up structure 12 and the solder balls 125 to the external device.
As described above, in the package member of the prior art, the circuit layer 122 is electrically connected via the conductive vias 120 directly to the semiconductor chip 11, and the conductive vias 120 are formed by plated copper in vias formed in an insulating layer, the vias being fully filled by the plated copper. However, because coefficients of thermal expansion (CTE) of composed components (such as the insulating layer and a protection layer for protecting the semiconductor chip) surrounding the conductive vias 120 are mismatched, thermal expansion of the composed components are different from each other. In result, a thermal stress is produced in the package member, the formed circuit structure is likely separated from the electrode pads 110 of the semiconductor chip 11 due to the thermal stress, and the package member is thus malfunctioned.
Moreover, in order to satisfy the demand of fine pitch and reduction of signal transmission route, the conductive vias 120 for connection of circuitry are formed to have a stack structure. However, because the composed units surrounding the conductive vias 120 have different CTEs, and thermal stress produced in the package member are therefore mismatched, the circuit structure is easily separated from the electrode pads 120 of the semiconductor chip 11. In result, the demand of fine pitch can not be attained and the package member has poor reliability.
Therefore, how to provide an electric connection structure of a circuit board embedded with semiconductor chips to overcome the drawbacks of the prior art has becoming one of the most urgent issues in the art.